Tulisan FPGA 2

MULTIPLEXER

Multiplexer berfungsi untuk memilih output dari beberapa input berdasarkan input pada kaki selectornya. Multiplexer memiliki rangkaian logika sebagai berikut :

Logika Programmer : 

library ieee;
use ieee.std_logic_1164.all;

entity kepletex is     -- mendefinisikan entity "kepletex"
port(             
a,b,c,d,s1,s2: in bit; -- terdapat 4 port input, 2 selector, dan 1 output
y:out bit);
end kepletex;

architecture mux_arch of kepletex is
begin
proc: process is
begin
if (s1='0' and s2='0') then y <= a;
else if (s1='0' and s2='1') then y <= b;
else if (s1='1' and s2='0') then y <= c;
else if (s1='1' and s2='1') then y <= d;
end if;
end process proc;
end mux_arch;

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Paket yang terdapat pada Library IEEE dan STD 

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

PACKAGE my_package IS

CONSTANT ADDER_WIDTH : integer := 5;

CONSTANT RESULT_WIDTH : integer := 6;

SUBTYPE ADDER_VALUE IS integer RANGE 0 TO 2 ** 

ADDER_WIDTH - 1;

SUBTYPE RESULT_VALUE IS integer RANGE 0 TO 2 ** 

RESULT_WIDTH - 1;

END my_package;

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE work.my_package.ALL;

ENTITY addsub IS

PORT

(

a: IN ADDER_VALUE;

b: IN ADDER_VALUE;

addnsub: IN STD_LOGIC;

result: OUT RESULT_VALUE

);

END addsub;

ARCHITECTURE rtl OF addsub IS

BEGIN

PROCESS (a, b, addnsub)

BEGIN

IF (addnsub = ‘1′) THEN

result ELSE

result END IF;

END PROCESS;

END rtl;

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Paket Library WORK 

LIBRARY IEEE;

USE IEEE.std_logic_1164.all;

USE IEEE.std_logic_arith.all;

USE IEEE.std_lodic_unsigned.all;

LIBRARY lpm;

USE lpm.lpm_components.all;

USE WORK.sigdec1.ALL